1. Field of the Invention
This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the disclosure relates to a semiconductor device including a capacitor that has a storage electrode having greatly improved electrical characteristics and structural stability, and a method of manufacturing a semiconductor device having such a capacitor.
2. Description of the Related Art
In general, semiconductor memory devices such as dynamic random access memory (DRAM) devices can store data or information therein. The data or information may be stored in the semiconductor memory devices, and the data or information may also be read from the semiconductor memory devices. A typical single unit memory cell of the semiconductor memory device includes one capacitor and one transistor. The capacitor of the semiconductor memory device typically includes a storage electrode, a dielectric layer, and a plate electrode. To improve a storage capacitance of the semiconductor memory device, a capacitor with a high capacitance value is required.
As semiconductor memory devices become highly integrated, the area of the unit memory cell of the semiconductor memory device is decreased. To ensure a sufficient storage capacitance of the semiconductor memory device, the capacitor may have various shapes such as a box, a cylinder, etc. However, as a design rule for the semiconductor memory device decreases, the aspect ratio of the capacitor increases because the capacitor must be formed in a correspondingly limited unit area. The aspect ratio is defined as the ratio between a height of the capacitor and a width of the capacitor. As a result, adjacent capacitors having a high aspect ratio may lean against each other so that the adjacent capacitors are electrically connected with each other, thereby causing a two-bit short between the adjacent capacitors.
To overcome the above problem, cylindrical capacitors having a stepped sidewall and methods for fabricating the same are disclosed in U.S. Pat. No. 5,610,741 issued to Hwang, et al.
FIGS. 1 to 4 are cross-sectional diagrams illustrating a conventional method for forming cylindrical capacitors having stepped inner side faces.
Referring to FIG. 1, storage node contact holes (not shown) that expose contact regions are formed through an insulating interlayer 1 positioned on a semiconductor substrate.
Storage node contact plugs are formed in the storage node contact holes, respectively. A nitride etching stop layer 6 is then formed on upper faces of the storage node contact holes and on an upper face of the insulating interlayer 1.
A lower mold layer 9 and an upper mold layer 12 are successively formed on an upper face of the etching stop layer 6. Here, the lower mold layer 9 includes a material that has an etch rate greater than that of a material included in the upper mold layer 12 with respect to an etching solution including hydrogen fluoride (HF). For example, the lower mold layer 9 may be formed using boro-phosphor silicate glass (BPSG) or phosphor silicate glass (PSG), etc., and the upper mold layer 12 may be formed using undoped silicate glass (USG) or tetra ethyl ortho silicate (TEOS), etc.
The upper mold layer 12, the lower mold layer 9, and the etching stop layer 6 are successively patterned to form preliminary storage node holes 15 that expose the storage node contact plugs 3. Here, upper portions of the preliminary storage node holes 15 have diameters greater than those of lower portions of the preliminary storage node holes 15.
Referring to FIG. 2, exposed inner side faces of the lower mold layer 9 in the preliminary storage node holes 15 are isotropically etched to thereby form storage node holes 18. Lower portions of the storage node holes 18 have diameters greater than those of the preliminary storage node holes 15. As a result, the storage node holes 18 have stepped inner side faces.
Referring to FIG. 3, a conductive layer 21 and a hemi-spherical grain (HGS) silicon layer 24 that covers the mold layer and inner faces of the storage node holes 18 are successively formed. A sacrificial layer 27 is then formed to thereby fill the storage node contact holes 18.
Referring to FIG. 4, the sacrificial layer 18, the HGS silicon layer 24, and the conductive layer 21 are removed until the upper face of the upper mold layer 12 is exposed to thereby form a conductive layer pattern 30 and a HSG silicon layer pattern 33 in the storage node contact holes 18. Sequentially, the upper mold layer 12 and the lower mold layer 9 are successively removed to thereby form storage electrodes 36 that include the conductive layer pattern 30 and the HGS silicon layer pattern 33. Here, the storage electrodes 36 have stepped inner side faces.
Upper portions of the storage electrodes 36 may be thinner during several etching processes for forming the storage electrodes 36 of capacitors. Lower portions of the storage electrodes 36 nay be etched once or twice, whereas the upper portions of the storage electrodes 36 may be etched at least three times. As a result, the upper portions of the storage electrodes 36 may have thicknesses that are much less than those of the lower portions of the storage electrodes 36. Because the thicknesses of the upper portions of the storage electrodes 36 are relatively thin compared to the lower portions of the storage electrodes, the electrical characteristics of the upper portions of the storage electrodes 36 may deteriorate. In addition, because the storage electrodes 36 having the thin upper portions are structurally unstable, the upper portions of the storage electrodes 36 may become bowed or deformed. Thus, the structural stability of capacitors that include the storage electrodes 36 may deteriorate. To overcome the bowing, stacked capacitors are disclosed in Japanese Laid Open Patent Publication No. 2003-224210.
FIGS. 5 to 8 are cross-sectional diagrams illustrating a method for forming stacked capacitors according to Japanese Laid Open Patent Publication No. 2003-224210.
Referring to FIG. 5, an insulating interlayer 45 is formed on the semiconductor 42 including underlying structures such as bit lines (not shown) and contact regions (not shown). Contact holes (not shown) are formed to expose the contact regions.
Contact plugs 48 are formed in the contact holes. A first etching stop layer 51, a first insulation layer 54, a second etching stop layer 57, and an antireflective 63 are successively formed on an upper face of the contact plugs 48 and on an upper face of the insulation inter layer 45.
A photoresist pattern 66 is formed on the antireflective coating 63. The antireflective coating 63, the second insulation layer 60, the second etching stop layer 57, the first insulation layer 54, and the first etching stop layer 51 are successively etched to form openings 69 that expose upper faces of the contact plugs 48.
Referring to FIG. 6, the photoresist pattern 66 and the antireflective coating 63 are removed. A first conductive layer 72 is then formed on an upper face of the conductive layer 60 and on inner faces of the openings 69.
A third insulation layer is formed on an upper face of the first conductive layer 72 to thereby fill the openings 69. The third insulation layer is partially etched to thereby form a third insulation layer pattern 75 in the openings 69.
Referring FIG. 7, the first conductive layer 72 is partially etched. The third insulation layer pattern 75 and the second insulation layer 60 are then removed to thereby form storage electrodes 78.
Referring to FIG. 8, a dielectric layer 81 and a plate electrode 84 are successively formed, and cover a partially exposed upper face of the second etching stop layer 57 and partially exposed faces of the storage electrodes 78. As a result, stacked capacitors 87 are formed.
Because the first insulation layer 54 and the first etching stop layer 51 are disposed between the stacked capacitors 87, the storage electrodes 78 are not fully used. As a result, the capacitances of the stacked capacitors 87 may be reduced. That is, because outer side faces of lower portions of the storage electrodes 87 are not covered with the dielectric layer 81 and the plate electrode 84, the lower portions of the storage electrodes 87 may not contribute to the capacitances of the capacitor.
In addition, because the storage electrodes 78 are formed by several etching processes, upper portions of the electrodes 78 may be thinner. As a result, the upper portions of the storage electrodes 78 may still become bowed or deformed.
Embodiments of the invention address these and other disadvantages of the conventional art described above.